CRIHAN  - Mars 2001
Outils d’optimisation - Page 21
3- D. perfex : analyse compilation en -O2
•L1 (n = 20), L2 (n = 300) et MEM (n=1000)
•
•                                                    Based on 195 MHz IP27
•                                                       MIPS R10000 CPU
•                                                       CPU revision 2.x
•                                                                                                                        Typical      Minimum      Maximum
•   Event Counter Name                                      Counter Value   Time (sec)   Time (sec)   Time (sec)
•===============================================================================================================
• 0 Cycles..................................................  20896529744   107.161691   107.161691   107.161691
•16 Cycles..................................................  20896529744   107.161691   107.161691   107.161691
•25 Primary data cache misses...............................       157632     0.007283     0.002280     0.007283
•26 Secondary data cache misses.............................         1312     0.000508     0.000332     0.000565
•23 TLB misses..............................................           16     0.000006     0.000006     0.000006
•
• 0 Cycles..................................................  38046735392   195.111464   195.111464   195.111464
•16 Cycles..................................................  38046735392   195.111464   195.111464   195.111464
•25 Primary data cache misses...............................   3499224576   161.682120    50.604171   161.682120
•23 TLB misses..............................................      5637952     1.968657     1.968657     1.968657
•26 Secondary data cache misses.............................       413152     0.159964     0.104580     0.177973
•
• 0 Cycles..................................................  21595891808   110.748163   110.748163   110.748163
•16 Cycles..................................................  21595891808   110.748163   110.748163   110.748163
•23 TLB misses..............................................    249980160    87.287944    87.287944    87.287944
•25 Primary data cache misses...............................   1318855728    60.937898    19.072683    60.937898
•26 Secondary data cache misses.............................     47711120    18.472767    12.077030    20.552482